Job Title

Key ResponsibilitiesFull chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysisFull chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing.Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPFRTL2GDSII design implementation and flow debug top down or bottoms up at chip levelPPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia and other critical sub-systemsLow Power signoff like Static and Dynamic power analysis at top level and/or sub-system levelFull chip / sub system level Clock tree synthesis and advanced clock tree implementation.Physical design and timing methodology development on a particular node as well as for a specific SOCAutomation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOCHands-on in reference flows, excellent debugging skills.Expertise in FC (Fusion Compiler)/Innovas Physical Design flows/methodologies or equivalent tools.Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, AnsysRedhawk on EMIR, PT-PX for Power signoff, CaliberExperience in 22 FDX FDSOI/ FinFeT 5nm & below technologies.