Job Title

Location: Hyderabad/Bangalore Type of Job: Full-time Mode -Onsite About Krutrim: High-Level Abstract of Krutrim's Next-Generation Silicon Design At Krutrim , we are pushing the boundaries of AI computing by designing a state-of-the-art, next-generation AI accelerator —a purpose-built silicon architecture optimized for AI training and inference at scale. Our RTL design is at the heart of this innovation, delivering unparalleled performance, energy efficiency, and scalability for the most demanding AI workloads. Our cutting-edge microarchitecture is tailored to accelerate multimodal AI models spanning text, voice, and vision. We are integrating custom compute engines , high-bandwidth memory interfaces, and ultra-low-latency interconnects to power real-time AI applications. With a highly parallel and programmable architecture , our silicon is designed to support next-generation LLMs, computer vision, and speech recognition , unlocking new frontiers in AI-driven innovation. At Krutrim , you will have the opportunity to work on: Custom AI compute cores designed for massive parallelism and efficiency High-speed interconnects and chiplet-based architectures for scalability Innovative memory hierarchies to minimize bottlenecks in AI processing Low-power design techniques for edge and cloud deployments Next-generation RTL design using the latest EDA tools and methodologies We are building India’s first AI-driven silicon that will power AI research, enterprises, and startups across the globe. If you're passionate about RTL design, computer architecture, and AI accelerators , come be a part of a team that is shaping the future of AI hardware! Join us at Krutrim and build the future of AI computing! SOC RTL design, Microarchitecture Lead Responsibilities: Micro architect, Design and Deliver RTL for (one of the following): Clock/ Reset/ Power Management SoC Fabrics, Protocol Bridges Fuse, Boot, Security Co-develop micro architecture with SoC architects to meet a specific requirement of the device. Write MAS document, drive alignment with reviews to sign-off. Develop and deliver RTL, UPF, (co-develop) timing constraints with all QC checks. Work with SoC lead to integrate the design, review/ signoff Verification plan. Review DFT and PD implementation to sign-off. Skills: Proven track record of having Micro architected, Designed and Delivered one of the following focus areas for a complex SoC to production: Clock/ Reset/ Power Management SoC Fabrics, Protocol Bridges Fuse, Boot, Security RTL design process: Specifying microarchitecture, developing RTL, linting, UPF coding, delivering synthesizable RTL, guiding Verification, DFT and PD implementations of the design. Awareness in comprehensive validation techniques of the specific design domain. Ability to review and signoff implementation of the design. Hands-on experience working with version control systems. Work with the FW development team for the design – as required. Scripting experience for efficiency and quality. Education & Experience: CS/ EE/ EC Engineering Graduate or postgraduate with +10 years of relevant experience.