Job Title

Role Description This is a full-time on-site role for a Senior Layout Engineer located in Bengaluru. The Senior Layout Engineer will be responsible for layout design and physical verification. The role involves working on analog layouts and ensuring comprehensive physical design and verification across projects. The engineer will collaborate closely with cross-functional teams to deliver next-generation semiconductor solutions. Key Responsibilities: Work with remote designers to plan chip floorplans and design Optimization for PLL,RX,TX or OPAMPS. Optimize parasitics, area, and performance Read foundry docs to solve DRC/latch-up issues Do custom layout in Virtuoso and ensure LVS/DRC clean Handle chip-level design (bump, pad, ESD) Communicate clearly via docs and video calls Requirements: 5+ to 8 Years IC layout experience 45 days or Immediate joining(Highly Preferred) Strong in Virtuoso, Calibre, SkillCad Good communication and planning skills