Job Title

The candidate will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compression. Work with physical Designers to validate the DFT timing constraints, RTL Designers to verify test design rules, Test Engineers to bring up the patterns on the ATE Automated Test Equipment and help develop and deploy DFT methodologies for our next generation products. Key Qualifications MSEE or equivalent experience 7+ years of experience in DFT or related domains You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development Strong programming and scripting skills in Perl, Python or Tcl desired