Job Title

Would you like to be part of the Exceltic experience, a company with a people-centered strategy?If you're looking to join cutting-edge projects in a fast-growing tech company, we want to meet you!At Exceltic, we are looking for an experienced FPGA Verification Engineer with more than 7 years of expertise in developing robust unit, regression, and integration testing systems based on UVM. Join our team in Madrid, Spain!ResponsibilitiesDevelop a test system based on the UVM methodology.Implement RTL simulations and IP designs for functional system-level verification of our FPGA-based designs.RequirementsAdvanced knowledge of UVM methodology.Strong expertise in SystemVerilog and UVM.Solid understanding of SystemC, C/C++, Python/Perl.Experience in developing and establishing verification methodologies (DV).Ability to develop testbenches in SystemVerilog using UVM methodology from scratch.Experience in configuring and maintaining the hardware infrastructure required for the verification system.Experience in C/C++ modeling for design verification.Strong test planning and problem-solving skills.Hands-on experience with UVM verification in AXI-based systems and high-speed communication protocols such as PCIe and Ethernet.Knowledge of RF and DSP fundamentals.Experience in RTL design for hardware description and circuit implementation.Experience in developing scalable and portable testbenches.Experience with verification methodologies and tools, including simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations.Familiarity with Cadence Xcellium.What do you need?