Job Title

Why Multi Phase PowerMPP product line offers high performance, innovative and cost-effective power solutions for a broad range of customer applications in enterprise, communications and automotive which include multiple phase DC/DC controllers, smart power stages. In MPP, our mission is to power the processors that power AI & future servers. Target platforms include Intel, AMD, ARM, NVidia and custom ASIC/FPGAs from various vendors. We are looking for an Analog Design Lead / Senior Design Engineers who have the passion and excitement to grow, innovate, take an active role in designing high current Power stage ICs. This is a fast paced, results driven environment that requires broad knowledge, creativity and excellent interpersonal skills on a daily basis. The engineers have to collaborate with the broader IC development teams (Layout, DV, Test, System Validation & Product Engineers) to deliver products to the market which are compelling, competitive, cost-conscious, manufacturable, and importantly, successful in growing TI's business Basic Qualifications:Bachelor's/Master's Degree in EE 5+ Years experience in Analog DesignBasic Job Qualifications:Strong competency in transistor level design and implementation of various Analog functions.Strong track record of taping out multiple complex IPs to manufacturing.Experience in designing analog circuits like operational amplifiers, Band-gap references, comparators, chargepump, level shifters.Experience on working with digital designers, providing and defining specs and state machineExperience on leading a full chip development /owning a sub-system for a complex chip.Top-level integration, Block-level verification across PVT, Statistical Mismatch, layout guidance.Strong silicon debugging skill to solve complex silicon problems through simulation and bench testing.Good communication, presentation skills and should be a team player.Preferred qualification:Experience on BCD process is a plus.Experience in switching DC-DC converter design, buck, buck-boost, control loop is preferred.Experience on design and layout of gate drivers, LDMOS, fault systems is highly desirable.Understanding of chip level ESD/LU, EM requirements.Good knowledge of IC Packaging and production test methodologies.Primary responsibilities:Lead the full chip development with product ownership from definition to release to manufacturing. Work closely with marketing and systems teams to define product specifications. Work closely with other designers and technologist in defining various architecture.Derive block level specification and select the topology based on product requirements.Generate top-level simulation plan and collaborate with verification engineer for best coverage.Work closely with Layout engineer to get optimized IC layout by minimizing parasitic elements.Validate Silicon, assist characterization and participate in De-bug processMentor 1-2 people