Hi All, Greetings from Eximietas...! Position: Design for Test (DFT) Engineer/Lead Locations: (Visakhapatnam, Bangalore & Ahmedabad) Mode of Work: On-site Exp: ~5+ Years This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Job Overview: The company is seeking an experienced and highly skilled Senior SoC Design for Test Engineer with a minimum of 5 years of hands-on experience in SoC Design for Test . As a key team member , the engineer will play a pivotal role in ensuring the robustness and correctness of cutting-edge System on Chip (SoC) designs . Job Description: Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution of verification plans . Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs , including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI , and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, and HBM . Conduct Gate-level simulations and power-aware verification using Xprop and UPF . Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams . Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers. Manage and lead a dynamic team of verification engineers , fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive. Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines . Adhere to quality standards, test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence , including VCS and Xsim . Integration of third-party VIPs (Verification IP) from Synopsys and Cadence . Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.
Job Title
Design for Test (DFT) Engineer/Lead