Experience-8+ years Innovus expertise in designing Floorplan for SoC Must have a knowledge and implementation strategies to create an IO ring in accordance design specification Have a deep knowledge on ESD, latch-up etc for foundry requirements and placement strategies Should have a hierarchical design implementation knowledge which include partitions/HMs/tiles push down to each core/tile Should have a knowledge on feed through planning and implementation. PG creation and push down methodology's knowledge and implementation Should have a knowledge on Analog components and their requirements in placements according to design specifications RDL knowledge and working with packaging is a must for SoC floorplan designer PV clean-up on floorplan and self-derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements any Deep scripting knowledge is essential Soft skills working with Packaging, design team and HM owners is essential
Job Title
SOC/ Fullchip Floorplan Lead