Job Title

Senior engineer -AMS/IO layout Job Locaiton: hyd and Noida. Exp : 4 to 15 yrs. Job Description Excellent work experience in IO Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Hands on experience in any or multiple critical blocks IO blocks like GPIO ,SDIO ,DDR IO etc along with the SERDES blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of Analog Layout concepts (e.g. Matching, Electro-migration, Latch-up, Coupling, Crosstalk, IR-drop, Active and Passive parasitic devices etc. Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area Excellent hands on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL Responsible for timely and quality execution of Custom Layout design Excellent communication skills and proactive at work Good to have: High learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Knowledge of Skill code layout automation