Job Title

DFT Lead/Manager /Senior ManagerHyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ BangaloreA US based well-funded product-based startup looking for Highly talented DFT Manager / Lead / Engineers for the following roles.Job Overview:The DFT Manager is responsible for leading a team of engineers to develop and implement cutting-edge Design for Testability solutions to ensure the manufacturability, quality, and reliability of memory and storage products. This role bridges the gap between design, manufacturing, and testing by integrating test strategies into the design phase to enhance product performance and cost-efficiency.Key Responsibilities:Leadership & Team Management:Build, Lead and mentor a team of DFT engineers to deliver high-quality test solutions.Drive innovation in DFT methodologies and promote their adoption across design teams.Manage project schedules, deliverables, and resource allocation for DFT activities.DFT Implementation:Define and implement industry-standard DFT architectures (e.g., scan, BIST, boundary scan).Collaborate with design teams to integrate DFT features into ASIC and memory products.Ensure test coverage requirements are met for functional and structural testing.Collaboration Across Teams:Work closely with product design, test engineering, and manufacturing teams to align DFT strategies with product goals.Facilitate seamless integration of test solutions into the product development lifecycle.Optimization & Problem-Solving:Analyze and resolve test-related issues during development and production.Drive yield improvement and test time reduction through innovative test solutions.Provide feedback on design improvements for enhanced testability and reliability.Process Development:Develop and maintain DFT guidelines, flows, and best practices for product lines.Monitor advancements in DFT technologies and incorporate them into processes.Ensure compliance with industry standards and regulatory requirements.Skills & Qualifications:Technical Skills:Strong expertise in DFT methodologies and tools, including:Scan insertion and ATPG (Automatic Test Pattern Generation).Built-In Self-Test (BIST) for memory and logic.JTAG/IEEE 1149.x boundary scan.Knowledge of semiconductor manufacturing processes and yield analysis.Familiarity with digital design principles (RTL, Verilog/VHDL, synthesis).Proficiency in EDA tools for DFT implementation (e.g., Synopsys, Cadence, Mentor Graphics).Experience with scripting/programming (e.g., Python, Perl, TCL) for automation.Leadership & Communication Skills:Proven ability to manage and mentor engineering teams.Strong project management and multitasking skills.Excellent communication skills to collaborate with cross-functional teams and present technical concepts to stakeholders.Experience:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.12-20 years of experience in DFT, with at least 3 years in a leadership or managerial role.Experience with memory technologies (e.g., DRAM, NAND, NOR) is a strong plus.Key Deliverables:Implementation of robust DFT strategies for new product introductions.Reduction in test time and improvement in test coverage.Enhanced first-pass success rates for new designs.Continuous improvement of DFT processes to meet market and technology demands.Contact:UdayMulya Technologiesmuday_bhaskar@"Mining The Knowledge Community"